This invention relates to circuit simulation and, in particular, to simulation of complex analog circuits, such as production power supplies.
This invention solves problems inherent in the simulation process of design verification testing of complex analog circuits, such as those designed and used by the power electronics industry. In many cases, the barriers to using simulation as an integral part of the design process have heretofore been insurmountable. Even for relatively small circuits (e.g., 100 components), the preparation time required to obtain the first usable results exceeded any practical allotment in a product development schedule. A brute-force modeling strategy that entails always using the most complex device model served in the past to reduce preparation time and tended to maximize the central processing unit (CPU) computation time required to carry out an individual simulation.
Moreover, the complexity of a typical production electrical circuit schematic further increased the CPU time required to carry out an individual simulation to the extent that the simulation time often exceeded any practical time budget. Using these strategies to carry out a sufficient number of tests to adequately characterize the performance of a typical circuit design could easily exceed 30 days of CPU time. In some cases, a sufficiently complex complete production schematic, together with the additional mathematical difficulty resulting from a brute-force modeling strategy, made it impracticable to obtain any simulation results whatsoever.
These barriers are exacerbated in the simulation of full production power supplies. Challenges inherent in the simulation of full production power supplies stem from the presence of many energy storage components, which result in a consequent large range of time constants and many energy transfer cycles to reach steady state operation.
If these barriers to simulation can be overcome, the potential economic benefit using simulation to improve the development process in the power electronics industry could be very significant. By simulating the production schematic circuit diagram, a majority of the design errors typically imbedded in a first prototype hardware model can be detected before printed circuit board layout is undertaken. Simulation can result in far fewer design errors becoming embedded initially in the prototype hardware and a consequent reduction in the number of hardware prototype iterations and overall significant reduction in product development cycle time.
The following is a set of definitions of terms used throughout the patent application:
A xe2x80x9cdevicexe2x80x9d is a specific electrical hardware component, software implementation, or circuit that may be represented by a single element or component. Examples of xe2x80x9cdevicesxe2x80x9d include a 5600 xcexcF, 10 volt, aluminum electrolytic output capacitor; a 1N4148 general small signal PN rectifier; and a snubber circuit that compensates for adverse parasitic inductance in a transformer. A xe2x80x9cdevicexe2x80x9d has nodes, often referred to as leads, for connection to nodes of other devices in the system or subsystem. A connection of device nodes is referred to as a xe2x80x9ccircuit node.xe2x80x9d
A xe2x80x9cdevice modelxe2x80x9d is a mathematical representation (which includes either one of or both analytical and numerical models) of the electrical behavior of a specific device when subject to one or more specific electrical conditions. A typical device may have multiple device models of varying complexity representing the behavior of the device for various purposes. The term xe2x80x9cdevice model levelxe2x80x9d distinguishes different device models of a given device.
A xe2x80x9csystemxe2x80x9d is a complete electrical or electronic system of devices under test. A xe2x80x9csystemxe2x80x9d may be represented by a production schematic diagram illustrating the connection of device nodes to system circuit nodes. For purposes herein, a xe2x80x9csystemxe2x80x9d does not necessarily include sources and loads that are not part of the production circuit.
A xe2x80x9csubsystemxe2x80x9d is a portion of a system for which the user desires meaningful simulation results.
A xe2x80x9cnetlistxe2x80x9d is a set of statements that define devices and the connection of device nodes to circuit nodes in a system or subsystem.
A xe2x80x9cproduction netlistxe2x80x9d is a netlist of the production circuit without simplification for simulation purposes. A production netlist may, for example, be the result of a computer-aided design (CAD) schematic capture program.
An xe2x80x9cattribute clubxe2x80x9d is a collection of devices that exhibit a common attribute, which may be electrical, mechanical, magnetic, or radiant in nature. The members of an xe2x80x9cattribute clubxe2x80x9d normally have a common specified device model level for at least one test-type objective.
A xe2x80x9cfunction clubxe2x80x9d is a collection of devices that operate together to perform a specified function. Attribute clubs and function clubs are sometimes collectively referred to as xe2x80x9cclubs.xe2x80x9d
A xe2x80x9ctest-type objectivexe2x80x9d is a common simulation objective of a test or collection of tests performed on a test-type deck, which is defined below.
A xe2x80x9ctest-type selection processxe2x80x9d is a process applied to a system or subsystem netlist by which a set of function clubs is used to select an appropriate netlist for simulation consistent with a given test-type objective.
A xe2x80x9ctest-type model selection processxe2x80x9d is a process applied to the group of devices resulting from the test-type selection process to select device models at a device model level consistent with a given test-type objective.
A xe2x80x9ctest-type deckxe2x80x9d is the result of a test-type selection process and a test-type model selection process. A xe2x80x9ctest-type deckxe2x80x9d is a description of the interconnections of a collection of devices, together with the device models at a selected model level, formulated to carry out a common test-type objective.
An xe2x80x9cexternal componentxe2x80x9d refers to any external simulation test component that is added to a test-type deck to enable simulation of the system or subsystem under the desired operating conditions. Examples of external components include energy sources, active and passive loads, and active and passive components that provide excitation input signals such as signals to adjust, enable, or disable certain circuit functions.
A xe2x80x9csimulation deckxe2x80x9d is the result of combining a test-type deck with the appropriate external components and other instructions for the simulation engine, such as duration of simulation and requests to produce certain specific circuit waveforms. Test-type decks and simulation decks are sometimes referred to in shorthand manner as xe2x80x9cdecks.xe2x80x9d
The present invention dramatically reduces each of these barriers to simulation of complex analog circuits. The invention reduces the preparation time not by using a brute force modeling strategy but by permitting a skilled user to formulate a simulation strategy that can combine a modeling strategy, a deck extraction strategy, and a comprehensive suite of pre-engineered simulation tests that fully characterize a system under test. This pre-engineered simulation strategy can be applied to a new system very quickly in an automated fashion by a circuit designer having much less simulation experience than that of the skilled user who formulated the simulation strategy.
The invention reduces the CPU time required for each test by allowing a skilled user to encode a device modeling strategy and a deck extraction strategy that effectively minimize the CPU time required to achieve a given simulation objective. In other words, for a given simulation objective, a skilled user chooses for each element implemented in a simulation a device model of minimum complexity that achieves a desired level of simulation accuracy and extracts a portion of the complete production schematic that achieves the desired level of simulation accuracy.
The invention reduces dramatically the effort required of a user to compose a required number of inputs to run a specified number of simulation tests and reduces dramatically the amount of CPU time required to run these tests. Coverage of 300-600 tests in fewer than 12 hours is achievable with the present invention, as compared with running one test in 24 hours or 500 tests in more than 30 CPU days, as is currently achievable with conventional techniques. As a result, this invention provides a new simulation capability that dramatically reduces the development interval for complex analog circuits and products implemented with them.